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ICX432DQF
Diagonal 6.67mm (Type 1/2.7) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras
Description The ICX432DQF is a diagonal 6.67mm (Type 1/2.7) interline CCD solid-state image sensor with a square pixel array and 3.24M effective pixels. Adoption of a 3-field readout system ensures small size and high performance. This chip features an electronic shutter with variable charge-storage time. R, G, B primary color mosaic filters are used as the color filters, and at the same time high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology. This chip is suitable for applications such as electronic still cameras, etc. 18 pin SOP (Plastic)
Pin 1
Features * Supports frame readout system * High horizontal and vertical resolution * Supports high frame rate readout mode : 30 frames/s, AF mode : 60 frames/s, 50 frames/s * Square pixel * Horizontal drive frequency: 24.3MHz * No voltage adjustments (reset gate and substrate bias are not adjusted.) * R, G, B primary color mosaic filters on chip * High sensitivity, low dark current * Continuous variable-speed shutter * Excellent anti-blooming characteristics * 18-pin high-precision plastic package
2
V
8 4 Pin 11 H 48
Optical black position (Top View)
Device Structure * Interline CCD image sensor * Total number of pixels: 2140 (H) x 1560 (V) approx. 3.34M pixels * Number of effective pixels: 2088 (H) x 1550 (V) approx. 3.24M pixels * Number of active pixels: 2080 (H) x 1542 (V) approx. 3.21M pixels diagonal 6.667mm * Number of recommended recording pixels: 2048 (H) x 1536 (V) approx. 3.15M pixels diagonal 6.592mm aspect ratio 4:3 * Chip size: 6.10mm (H) x 4.95mm (V) * Unit cell size: 2.575m (H) x 2.575m (V) * Optical black: Horizontal (H) direction: Front 4 pixels, rear 48 pixels Vertical (V) direction: Front 8 pixels, rear 2 pixels * Number of dummy bits: Horizontal 28 Vertical 1 (3rd field only) * Substrate material: Silicon
Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (HoleAccumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by Sony Corporation. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E02123A27
ICX432DQF
Block Diagram and Pin Configuration (Top View)
GND V3A V3B V5A V5B
2 B Gr B Gr B Gr B Gr Note)
V1
V2
V4
9
8
7
6
5
4
3
Gb R
B Gr B Gr B Gr B Gr
Gb R Gb R Gb R Gb R
Vertical register
Gb R Gb R Gb R
Horizontal register Note) : Photo sensor
10
11
12
13
14
15
16
17
18
H1
CSUB
VOUT
VDD
RG
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 Symbol V6 V5B V5A V4 V3B V3A V2 V1 GND Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Pin No. 10 11 12 13 14 15 16 17 18 Symbol VOUT VDD RG GND SUB CSUB VL H1 H2 Description Signal output Supply voltage Reset gate clock GND Substrate clock Substrate bias 1 Protective transistor bias Horizontal register transfer clock Horizontal register transfer clock
1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1F.
SUB
GND
-2-
H2
VL
V6
1
ICX432DQF
Absolute Maximum Ratings Item VDD, VOUT, RG - SUB V1, V3A, V3B, V5A, V5B - SUB Against SUB V2, V4, V6, VL - SUB H1, H2, GND - SUB CSUB - SUB VDD, VOUT, RG, CSUB - GND Against GND V1, V2, V3A, V3B, V4, V5A, V5B, V6 - GND H1, H2 - GND Against VL V1, V3A, V3B, V5A, V5B - VL V2, V4, V6, H1, H2, GND - VL Voltage difference between vertical clock input pins Between input clock pins H1 - H2 H1, H2 - V6 Storage temperature Guaranteed temperature of performance Operating temperature 1 +24V (Max.) when clock width < 10s, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply. Ratings -40 to +12 -50 to +15 -50 to +0.3 -40 to +0.3 -25 to -0.3 to +22 -10 to +18 -10 to +6.5 -0.3 to +28 -0.3 to +15 to +15 -6.5 to +6.5 -10 to +16 -30 to +80 -10 to +60 -10 to +75 Unit V V V V V V V V V V V V V C C C 1 Remarks
-3-
ICX432DQF
Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock Symbol VDD VL SUB RG Min. 14.55 Typ. 15.0 1 2 2 Max. 15.45 Unit V Remarks
1 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for the V driver should be used. 2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD.
DC Characteristics Item Supply current Symbol IDD Min. 5.0 Typ. 7.0 Max. 9.0 Unit mA Remarks
Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVH5, VVH6 VVL1, VVL2, VVL3, VVL4, VVL5, VVL6 Vertical transfer clock voltage VV VVH5 - VVH VVH6 - VVH VVHH VVHL VVLH VVLL VH Horizontal transfer clock voltage VHL VCR VRG Reset gate clock voltage VRGLH - VRGLL VRGL - VRGLm Substrate clock voltage VSUB 21.5 22.5 3.0 -0.05 0.5 3.0 3.3 0 1.65 3.3 3.6 0.4 0.5 23.5 Min. 14.55 -0.05 -0.2 -8.0 6.8 -0.25 -0.25 Typ. 15.0 0 0 -7.5 7.5 Max. Unit 15.45 0.05 0.05 -7.0 8.05 0.1 0.1 0.8 0.9 0.9 0.8 3.6 0.05 V V V V V V V V V V V V V V V V V V Waveform Diagram 1 2 2 2 2 2 2 2 2 2 2 3 3 3 4 4 4 5 Low-level coupling Low-level coupling Cross-point voltage High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL5 + VVL6)/2 VV = VVHn - VVLn (n = 1 to 6) VVH = (VVH1 + VVH2 + VVH3 + VVH4)/2 Remarks
-4-
ICX432DQF
Clock Equivalent Circuit Constants Item CV1 Capacitance between vertical transfer clock and GND CV3A, CV3B, CV5A, CV5B CV2, CV4, CV6 CV12 Capacitance between vertical transfer clocks CV23A, CV23B, CV45A, CV45B CV3A4, CV3B4, CV5A6, CV5B6 CV61 Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor Horizontal transfer clock series resistor CH1, CH2 CHH CRG CSUB R1, R2, R4, R6 R3A, R5A R3B, R5B RGND RH Symbol Min. Typ. 1280 640 400 510 50 260 100 40 70 8 1000 60 240 80 18 13 Max. Unit Remarks pF pF pF pF pF pF pF pF pF pF pF
V1 R1 CV12 CV61 R6 V6 CV5B6 CV1 CV6 CV5A6 CV2
V2 R2 CV23A R3A CV3A CV23B
CH1 CH2
RH
CHH
RH H2
V3A
H1
CV3B RGND R5B CV5B V5B CV4 CV5A CV45B CV45A R5A V5A
R3B V3B
CV3B4
CV3A4 R4 V4
Vertical transfer clock equivalent circuit -5-
Horizontal transfer clock equivalent circuit
ICX432DQF
Drive Clock Waveform Conditions (1) Readout clock waveform
100% 90%
M VVT 10% 0% tr twh tf 0V M 2
(2) Vertical transfer clock waveform
V1 VVH1 VVHH VVH VVHL VVHL VVHL VVHH V2 VVH2 VVHH VVH VVHL VVHL VVHH VVHH
VVL1 VVLH VVLL VVL V3A, V3B VVH3 VVHL VVHH VVH VVHL VVHL VVH4 VVHH V4 VVHH VVL VVLL
VVL2 VVLH
VVHH
VVH VVHL
VVHL
VVL3 VVLH VVLL VVL V5A, V5B VVHH VVHH VVHL VVH5 VVHL VVH VVHL VVH6 V6 VVHH VVHH VVHL VVL
VVL4 VVLH VVLL
VVH
VVL5 VVLL VVL
VVLH
VVLH
VVL6
VVLL
VVL
VVH = (VVH1 + VVH2 + VVH3 + VVH4)/4 VVL = (VVL5 + VVL6)/2 VV = VVHn - VVLn (n = 1 to 6)
-6-
ICX432DQF
(3) Horizontal transfer clock waveform
tr H2 90% VCR VH VH 2 10% H1 two VHL twh tf
twl
Cross-point voltage for the H1 rising side of the horizontal transfer clocks H1 and H2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks H1 and H2 is two. (4) Reset gate clock waveform
tr twh tf
RG waveform
VRGH
twl VRG Point A VRGLH VRGLL VRGLm VRGL
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval with twh, then: VRG = VRGH - VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform
100% 90%
M VSUB 10% VSUB 0% (A bias generated within the CCD) M 2 tf
tr
twh
-7-
ICX432DQF
Clock Switching Characteristics (Horizontal drive frequency: 24.3MHz) twh Item Readout clock Vertical transfer clock Horizontal transfer clock Symbol VT V1, V2, V3A, V3B, V4, V5A, V5B, V6 H1 H2 11 11 6 15 15 8 11 11 15 15 28 6.0 9.5 6.0 9.5 3 0.5 twl tr tf Unit s Remarks During readout When using CXD3400N
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.63 2.83 0.5 0.5
15
350 6.0 9.5 6.0 9.5 3 0.5
ns
ns tf tr - 2ns ns s During drain charge
Reset gate clock RG Substrate clock SUB
2.5 3.02
Item Horizontal transfer clock
Symbol H1, H2
two Min. Typ. Max. 10 15
Unit ns
Remarks
Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)
1.0 G 0.9 0.8 0.7 B R
Relative Response
0.6 0.5 0.4 0.3 0.2 0.1 0 400
450
500
550 Wave Length [nm]
600
650
700
-8-
ICX432DQF
Image Sensor Characteristics (horizontal drive frequency: 24.3MHz) Item G Sensitivity Sensitivity comparison Saturation signal Smear Video signal shading Dark signal Dark signal shading Line crawl G Line crawl R Line crawl B Lag Symbol Sg Rr Rb Vsat Sm SHg Vdt Vdt Lcg Lcr Lcb Lag Min. 165 0.46 0.33 420 -87.5 -78 -80 -70.5 20 25 10 8 3.8 3.8 3.8 0.5 Typ. 220 Max. 275 0.72 0.59 mV dB % mV mV % % % % Unit mV Measurement method 1 1 1 2 3 4 5 6 7 7 7 8 Ta = 60C
(Ta = 25C) Remarks 1/30s accumulation
Frame readout mode1 High frame rate readout mode Zone 0 and I Zone 0 to II' Ta = 60C, 5.0 frame/s Ta = 60C, 5.0 frame/s, 2
1 After closing the mechanical shutter, the smear can be reduced to below the detection limit by performing vertical register sweep operation. 2 Excludes vertical dark signal shading caused by vertical register high-speed transfer. Zone Definition of Video Signal Shading
2088 (H) 4 4 4 H 8 V 10 H 8
1550 (V)
Zone 0, I Zone II, II' V 10
4
Ignored region Effective pixel region
Measurement System
CCD signal output [A]
CCD
C.D.S
AMP
S/H
Gr/Gb channel signal output [B]
S/H
R/B channel signal output [C]
Note) Adjust the amplifier gain so that the gain between [A] and [B], and between [A] and [C] equals 1. -9-
ICX432DQF
Image Sensor Characteristics Measurement Method Measurement conditions (1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions, and the frame readout mode is used. In addition, VSUB Cont. is turned off. (2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb channel signal output or the R/B channel signal output of the measurement system. Color coding of this image sensor & Readout Gb B2 R Gb R B1 Gb R B Gr B Gr B Gr Gb R Gb R Gb R B Gr B Gr B Gr A1 A2 C1 C2 The primary color filters of this image sensor are arranged in the layout shown in the figure on the left (Bayer arrangement). Gr and Gb denote the G signals on the same line as the R signal and the B signal, respectively. For three frames readout, the A1 and A2 lines are output as signals in the A field, the B1 and B2 lines in the B field, and the C1 and C2 lines in the C field.
Horizontal register Color Coding Diagram
- 10 -
ICX432DQF
Readout modes 1. Readout modes list The following readout modes are possible by driving the image sensor at the timing specifications noted in this Data Sheet. Mode name Frame readout mode High frame rate readout mode AF mode NTSC mode PAL mode NTSC mode PAL mode NTSC mode PAL mode Frame rate 5.0 frame/s 5.0 frame/s 30 frame/s 25 frame/s 60 frame/s 50 frame/s Number of effective output lines 1550 (1st 517, 2nd 516, 3nd 517) 1550 (1st 517, 2nd 516, 3nd 517) 258 258 96 123
2. Frame readout mode, high frame rate readout mode Frame readout mode 1st field
13 12 11 10 9 8 7 6 5 4 3 2 1 VOUT R Gb R Gb R Gb R Gb R Gb R Gb R Gr B Gr B Gr B Gr B Gr B Gr B Gr VOUT 13 12 11 10 9 8 7 6 5 4 3 2 1
2nd field
R Gb R Gb R Gb R Gb R Gb R Gb R Gr B Gr B Gr B Gr B Gr B Gr B Gr VOUT 13 12 11 10 9 8 7 6 5 4 3 2 1
3rd field
R Gb R Gb R Gb R Gb R Gb R Gb R Gr B Gr B Gr B Gr B Gr B Gr B Gr
High frame rate readout mode
13 12 11 10 9 8 7 6 5 4 3 2 1 VOUT R Gb R Gb R Gb R Gb R Gb R Gb R Gr B Gr B Gr B Gr B Gr B Gr B Gr
Note) Blacked out portions in the diagram indicate pixels which are not read out. 1. Frame readout mode In this mode, all pixel signals are divided into three fields and output. All pixel signals are read out independently, making this mode suitable for high resolution image capturing. 2. High frame rate readout mode Output is performed at 30 frames per second by reading out 4 pixels for every 12 vertical pixels and adding 2 pixels in the horizontal CCD. The number of output lines is 258 lines. This readout mode emphasizes processing speed over vertical resolution.
- 11 -
ICX432DQF
3. AF The AF mode increases the frame rate by cutting out a portion of the picture through high-speed elimination of the top and bottom of the picture in high frame rate readout mode. This mode allows 1/60s and 1/50s output, so it is effective for raising the auto focus (AF) speed. In addition, the output line position and number of output lines are fixed. See the timing specifications for the cut-out region.
Top frame shift region
Cut-out region
Number of effective lines in high frame rate readout mode 258
Bottom high-speed sweep region
- 12 -
ICX432DQF
Definition of standard imaging conditions (1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. (2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. (3) Standard imaging condition III: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens (exit pupil distance -33mm) with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. G Sensitivity, sensitivity comparison Set to the standard imaging condition I. After setting the electronic shutter mode with a shutter speed of 1/100s, measure the signal outputs (VGR, VGb, VR and VB) at the center of each Gr, Gb, R and B channel screen, and substitute the values into the following formulas. VG = (VGr + VGb)/2 Sg = VG x 100 [mV] 30 Rr = VR/VG Rb = VB/VG 2. Saturation signal Set to the standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal outputs. 3. Smear Set to the standard imaging condition III. With the lens diaphragm at F5.6 to F8, first adjust the average value of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (Vsm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the following formula. Sm = 20 x log Vsm /
(
Gra + Gba + Ra + Ba 1 1 x 500 x 4 10
)
[dB] (1/10V method conversion value)
- 13 -
ICX432DQF
4. Video signal shading Set to the standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjusting the luminous intensity so that the average value of the Gr signal output is 150mV. Then measure the maximum value (Grmax [mV]) and minimum value (Grmin [mV]) of the Gr signal output and substitute the values into the following formula. SHg = (Grmax - Grmin)/150 x 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature of 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. Vdt = Vdmax - Vdmin [mV] 7. Line crawl Set to the standard imaging condition II. Adjusting the luminous intensity so that the average value of the Gr signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal lines (Glr, Glg, Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab). Substitute the values into the following formula. Lci = Gli x 100 [%] (i = r, g, b) Gai 8. Lag Adjust the Gr signal output value generated by the strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal amount (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) x 100 [%]
VD
V3A/V3B Light Strobe light timing
Gr signal output 150mV
Vlag (lag)
Output
- 14 -
ICX432DQF
Drive Circuit
0.1
-7.5V 3.3V
15V
1/35V 1 20 19 18 17 16 CXD3400N 15 14 13 12 11 0.1 0.1 100k
XSUB XV3 XSG3B XSG3A XV5 XSG5B XSG5A XV4 XV2 3.3V
2 3 4 5 6 7 8 9 10
1 0.1 2 3 4 5 CXD3400N XV1 6 7 XSG1 XV6 8 9 10
20 19 18 17 16 15 14 13 12 11 ICX432DQF (BOTTOM VIEW) 3.3/20V 0.1 1 2 3 4 5 6 7 8 9 2SC4250 CCD OUT 4.7k 0.1
V6
V4
V2
V5B
V5A
V3B
V3A
V1 VDD
SUB
CSUB
VOUT
GND
RG
H2
H1
VL
GND
VR1 (3.9k ) VSUB Cont.
0.01
18 17 16 15 14 13 12 11 10
H2 H1 RG 0.1
Substrate bias control signal VSUB Cont. Substrate bias SUB pin voltage
0.1 1M 3.3/16V 0.1
Mechanical shutter mode
GND tr 2ms Internally generated value VSUB
tf 17ms
Notes) Substrate bias control 1. The saturation signal level decreases when exposure is performed using the mechanical shutter, so control the substrate bias. 2. A saturation signal level equivalent to that for continuous exposure can be assured by connecting a VR1 grounding registor to the CCD CSUB pin. Drive timing precautions 1. Blooming occurs in modes (high frame rate readout, etc.) that do not use the mechanical shutter, so do not ground the connected VR1 resistor. 2. tf is slow, so the internally generated voltage VSUB may not drop to a sufficiently low level if the substrate bias control signal is not set to high level 30ms before entering the exposure period and the VR1 resistor connected to the CSUB pin is not grounded. 3. The blooming signal generated during exposure in mechanical shutter mode is swept by providing two fields or more of idle transfer through vertical register high-speed sweep transfer from the time the mechanical shutter closes until sensor readout is performed. However, note that the VL potential and the SUB pin DC voltage sag at this time. - 15 -
Drive Timing Chart (Vertical Sequence)
High Frame Rate Readout Mode Frame Readout Mode/Electronic Shutter Normal Operation
High frame rate readout mode
Exposure operation
Frame readout mode
High frame rate readout mode
VD
V1
V2
V3A
V3B
V4
- 16 -
B C OPEN CLOSE B signal output C signal output (1st) C signal output (2nd)
V5A
V5B
V6 E
SUB
B
TRG
Mechanical shutter
VSUB Cont. C signal output (3rd) Output after frame readout E signal output
ICX432DQF
CCD OUT
A signal output
B signal output
Note) High frame rate readout mode out signals of VSUB Cont. high period contain a blooming component and should therefore not be used. Apply 20 or more electronic shutter pulses at the start of exposure for the recording image. If less than 20 pulses are applied, the electronic shutter may occur a discharge error.
Drive Timing Chart (Vertical Sync)
NTSC/PAL Frame Readout Mode NTSC: 5.0 frame/s, PAL: 5.0 frame/s
Exposure period
VD
HD
41 44 564 588 629 746 749 632
1
NTSC
41 44 564 705 1269 1152 1410 1176 1451 1217 1454 1220
1
1975 1741
3 6 1 4 1546 1549
"b"
V1
V2 "a"
V3A
V3B
1 4 7 2 5 8
1547 1550
2 5 8 3 6 9
CCD OUT
ICX432DQF
Note) 2760fH, however, 588H, 1176H and 1764H in NTSC mode are 1500clk, 705H, 1410H and 2115H in PAL mode are 960clk.
1545 1548
- 17 -
V4 "c"
V5A
V5B
V6
SUB
TRG
Mechanical shutter
OPEN
CLOSE
VSUB Cont.
2115 1764
PAL
9
9
Drive Timing Chart (Readout)
NTSC/PAL Frame Readout Mode
"a" Enlarged
NTSC 44H PAL 44H
52 1 644 52
1296
H1
2760
308
V1
1420 1380 1460 350 476 392
V2
V3A/V3B
434 560
V4
1254 518
V5A/V5B
1338 602
644
52
2760 1
1546
2760
308
V1
266 392
V2
350 476
V3A/V3B
434 560
V4
1502 518
V5A/V5B
1338 1420 224 602
ICX432DQF
V6
644
1380 1460
1
- 18 -
V6
"b" Enlarged
NTSC 632H PAL 749H
H1
2760 1
644
Drive Timing Chart (Readout)
NTSC/PAL Frame Readout Mode
"c" Enlarged
NTSC 1220H PAL 1454H
52 1 644 52
1128 1254
H1
2760 644
476 560 518 602
V1
1212 1338
V2
1296
V3A/V3B
1420
V4
1380 1460 1086
- 19 -
1170
V5A/V5B
V6
2760 1
ICX432DQF
Drive Timing Chart (High-speed Sweep Operation)
NTSC/PAL Frame Readout Mode
HD
1
18 18 18 18 18 18 #2 #3 #1040
1
52
V1
V2
V3A/V3B
V4
V5A/V5B
V6
140
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
#1
Note) In the period of high-speed sweep operation, the rising of input clocks XV1, XV2, XV3, XV4, XV5 and XV6 to vertical transfer clock driver CD3400N should be delayed by 1 clock against the above timing chart.
52
- 20 -
ICX432DQF
Drive Timing Chart (Horizontal Sync)
NTSC/PAL Frame Readout Mode
2760
1
5
52
CLK
1 48 1 28 4 4 592
RG
SHP
SHD
1 1 1 1 1 1 126 298 1 126 168 214 1 126 252 130 1 336
V1
V2
- 21 -
1 1 382 1 88 1 378 1 172 1 1 83 88
V3A/V3B
1
V4
1 126
84
V5A/V5B
1
126
V6
378 1
42
H1 Ignored pixel 4 bits
Ignored pixel 4 bits
H2
SUB
644
ICX432DQF
Drive Timing Chart (Vertical Sync)
NTSC/PAL High Frame Rate Readout Mode NTSC: 30 frame/s, PAL: 25 frame/s
VD
HD
9 1 4 9 6 5 10 17 22 4 1 8 13 20 1525 1532 1537 1544 1549 9 29 25 32 34
NTSC
9 1 4
263 263
324 270
1
263 263
V1
V2
V3A
V3B
V4
V5A
V5B
V6
6 5 10 17 22 29 34 1529 1534 1541 1546
1534
1541
4
1
8
13
20
25
1532
1537
1544
Note) 3004fH, however, 270H in NTSC mode is 2734fH, 324H in PAL mode is 1708fH.
1549
32
CCD OUT
1546
324 270
PAL
1
- 22 -
ICX432DQF
Drive Timing Chart (Readout Portion)
NTSC/PAL High Frame Rate Readout Mode/AF Mode
H1
1 888 52 3004 888
1
52
1438
1611
1
V1
1540 1673 1
V2
1500 1642 1815 1580 1
V3A
1642
1815
1
- 23 -
1744 1877 1704 1407 1784 1846 1407 1846 1469 1908
V3B
1
V4
V5A
1
1
V5B
1
V6
ICX432DQF
Drive Timing Chart (Horizontal Sync)
NTSC/PAL High Frame Rate Readout Mode/AF Mode
3004
1
5
52
CLK
1 1 28 4 4 836
1
RG
SHP
SHD
1 1 1 1 1 1 93 1 243 1 279 93 1 93 1 93 128 181 1 279 1 93 1 93 190 119 1 279 1 252
V1
V2
V3A/V3B
48
V4
1 93
1
305
1
279 1 93
1
66
V5A/V5B
1
88 1
279 1
93 1
279 1
97 35
V6
1
150 1
279 1
93 1
279
H1 Ignored pixel 4 bits
Ignored pixel 4 bits
H2
1 83
1
5
SUB
3004
52
ICX432DQF
88
888
- 24 -
Drive Timing Chart (Vertical Sync)
AF Mode NTSC: 60 frame/s, PAL: 50 frame/s
VD
HD
1 4 9 1 4 25 28 9 9 25 25
NTSC
150 123
162 135 1
4
9
25
28
150 123
162 135 1
V1 Frame shift period High-speed sweep period Frame shift period
High-speed sweep period
V2
V3A
V3B
V4
V5A
V5B
V6 AF mode output signal
6
4
PAL
4
481 488
NTSC 96 lines PAL 123 lines
4
CCD OUT
485 490
6
- 25 -
ICX432DQF
Note) 3004fH, however, 135H in NTSC mode is 2869clk, and 162H in PAL mode is 2356clk.
Drive Timing Chart (High-speed Frame Shift Operation)
NTSC/PAL AF Mode
AF mode 20H
1 140 1 140
HD
31
V1
93 279 93 248
93
V2
93 279 93 186 124
- 26 -
62 31 #1 #2 AF: #78
V3A/V3B
155 93 279 93
V4
217 93 279 93
V5A/V5B
279 93 279 93
62
V6
279 93 279
ICX432DQF
Drive Timing Chart (High-speed Frame Sweep Operation) NTSC/PAL AF Mode
AF mode 11H
1 1 140
140
HD
12
V1
36 108 36 96
36
V2
36 108 36 72 48
- 27 -
24 12 #1 #2 AF: #114
V3A/V3B
60 36 108 36
V4
84 36 108 36
V5A/V5B
108 36 108 36
24
V6
108 36 108
ICX432DQF
ICX432DQF
Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero-cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operations as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.)
Cover glass
50N Plactic package Compressive strength
50N
1.2Nm Torsional strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. - 28 -
ICX432DQF
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD characteristics.
- 29 -
Package Outline
Unit: mm
18 pin SOP (400mil)
A 10 18 10
18
2.5
(0.6)
5.0
0.25 0.05
8.9
B
0 t o1 0
1.7
1.7 C
2.5 7.0
5.0
H 9 9 D B'
0.6 2.0
10.0 0.10
12.0 0.15
V
0.6
2.3
1
1
8.9 10.0 0.10
0.15
1. "A" is the center of the effective image area. 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 3. The bottom "C" of the package, and the top of the cover glass "D" are the height reference. 4. The center of the effective image area relative to "B" and "B'" is (H, V) = (5.0, 5.0) 0.07mm. 5. The rotation angle of the effective image area relative to H and V is 0.8.
1.0 0.10
0.46 0.38
1.11
0.30 0.15
2.50 0.15
- 30 -
2.5
7.0
0.3
M
6. The height from the bottom "C" to the effective image area is 1.20 0.10mm. The height from the top of the cover glass "D" to the effective image area is 1.30 0.15mm. 7. The tilt of the effective image area relative to the bottom "C" is less than 25m. The tilt of the effective image area relative to the top "D" of the cover glass is less than 25m. 8. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5. 9. The notch of the package is used only for directional index, that must not be used for reference of fixing.
ICX432DQF
PACKAGE MATERIAL
Plastic
LEAD TREATMENT
GOLD PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.5g
Sony Corporation
DRAWING NUMBER
AS-C15-02(E)

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